Performance and Efficiency Exploration of Hardware Polynomial Multipliers for Post-Quantum Lattice-Based Cryptosystems

The significant effort in the research and design of large-scale quantum computers has spurred a transition to post-quantum cryptographic primitives worldwide. The post-quantum cryptographic primitive standardization effort led by the US NIST has recently selected the asymmetric encryption primitive Kyber as its candidate for standardization and indicated NTRU, as a valid alternative if intellectual property issues are not solved. Finally, a more conservative alternative to NTRU, NTRUPrime was also considered as an alternate candidate, due to its design choices that remove the possibility for a large set of attacks preemptively. All the aforementioned asymmetric primitives provide good performances, and are prime choices to provide IoT devices with post-quantum confidentiality services. In this work, we present a comprehensive exploration of hardware designs for the computation of polynomial multiplications, the workhorse operation in all the aforementioned cryptosystems, with a thorough analysis of performance, compactness and efficiency. The presented designs cope with the differences in the arithmetics of polynomial rings employed by distinct cryptosystems, benefiting from configurations and optimizations that are applicable at synthesis time and/or run time. In this context, we target a use case scenario where long-term key pairs are used, such as the ones for VPNs (e.g., over IPSec), secure shell protocols and instant messaging applications. Our high-performance design variants exhibit figures of latency comparable to the ones needed for the execution of the symmetric cryptographic primitives also included in the Post-Quantum schemes. Notably, the performance figures of the designs proposed for NTRU and NTRU Prime surpass the ones described in the related literature

3D Finite Element Simulations of strip lines of a YBCO/Au Fault Current Limiter

Geometrical aspects of the design of fault current limiters (FCL) have a great impact on their performance. Recently, the University of Geneva have presented optimized geometries obtained by splitting the FCL into many small dissipative lengths in order to distribute the power along the device. We have performed 3D finite element method (FEM) simulations for studying the behavior of strip lines of a YBCO/Au FCL in AC nominal use (sinusoidal current at industrial frequency) up to 3 Ic. Particular attention has been paid to the mesh, due to the very large involved aspect ratios. The numerical results show a concentration of the electric field in the sharp corners. This results in very large power dissipation, which has been experimentally confirmed by wafer cracks during over-Ic tests. A new geometry, taking into account the length of the connecting path and the corner optimization, has been proposed. Finally, simulations coupling electromagnetic and thermal equations show the behavior of the device when a default occurs on the electrical network. This work is supported by the Swiss National Science Foundation through the National Center of Competence in Research “Materials with Novel Electronic Properties – MaNEP

Polymer-based photocathodes with a solution-processable cuprous iodide anode layer and a polyethyleneimine protective coating

Organic semiconductors are proven to efficiently drive photoelectrochemical water splitting

Optical modulation of excitation-contraction coupling in human-induced pluripotent stem cell-derived cardiomyocytes

Non-genetic photostimulation is a novel and rapidly growing multidisciplinary field that aims to induce light-sensitivity in living systems by exploiting exogeneous phototransducers. Here, we propose an intramembrane photoswitch, based on an azobenzene derivative (Ziapin2), for optical pacing of human-induced pluripotent stem cell-derived cardiomyocytes (hiPSC-CMs). The light-mediated stimulation process has been studied by applying several techniques to detect the effect on the cell properties. In particular, we recorded changes in membrane capacitance, in membrane potential (V-m), andmodulation of intracellular Ca2+ dynamics. Finally, cell contractility was analyzed using a custom MATLAB algorithm. Photostimulation of intramembrane Ziapin2 causes a transient V-m hyperpolarization followed by a delayed depolarization and action potential firing. The observed initial electrical modulation nicely correlates with changes in Ca2+ dynamics and contraction rate. This work represents the proof of principle that Ziapin2 can modulate electrical activity and contractility in hiPSC-CMs, opening up a future development in cardiac physiology

Chitosan gated organic transistors printed on ethyl cellulose as a versatile platform for edible electronics and bioelectronics

Edible electronics is an emerging research field targeting electronic devices that can be safely ingested and directly digested or metabolized by the human body. As such, it paves the way to a whole new family of applications, ranging from ingestible medical devices and biosensors, to smart labelling for food quality monitoring and anti-counterfeiting. Being a newborn research field, many challenges need to be addressed to realize fully edible electronic components. In particular, an extended library of edible electronic materials is required, with suitable electronic properties depending on the target device and compatible with large-area printing processes, to allow scalable and cost-effective manufacturing. In this work, we propose a platform for future low-voltage edible transistors and circuits that comprises an edible chitosan gating medium and inkjet printed inert gold electrodes, compatible with low thermal budget edible substrates, such as ethylcellulose. We report the compatibility of the platform, characterized by critical channel features as low as 10 µm, with different inkjet printed carbon-based semiconductors, including biocompatible polymers present in the picograms range per device. A complementary organic inverter is also demonstrated with the same platform as a proof-of-principle logic gate. The presented results offer a promising approach to future low-voltage edible active circuitry, as well as a testbed for non-toxic printable semiconductors

Metis: An Integrated Morphing Engine CPU to Protect Against Side Channel Attacks

Power consumption and electromagnetic emissions analyses are well established attack avenues for secret values extraction in a large range of embedded devices. Countermeasures against these attacks are approached at different levels, from modified logic styles, to changes in the software implementations. In this work, we propose a microarchitectural modification to a compact RISC-V SoC, the OpenTitan open source silicon root of trust, providing a code morphing countermeasure against power and electromagnetic emissions side channel attacks. Our approach allows the countermeasure to be applied transparently, without the need for any software modification to the cryptographic primitive running on OpenTitan. Our microarchitecture integration of a morphing engine also allows us to provide transparent protection to memory operations. We validate our approach through measurements on an actual FPGA prototype on a Xilinx Artix-7. Our integrated morphing engine increases the FPGA resource consumption by less than 8%, plus the resources required by an RNG of choice, with respect to the original OpenTitan SoC. Our design shows a side channel attack resistance improvement of at least 250× in the Measurements-To-Disclose metric with respect to the unprotected design. We benchmark the performance of our proposed architecture on all the ISO/IEC standard symmetric block ciphers, including, among the other AES, reducing the execution time overhead by 21× to 141× with respect to a continuously morphing software solution

An Efficient Unified Architecture for Polynomial Multiplications in Lattice-Based Cryptoschemes

The significant effort in the research and design of large-scale quantum computers has spurred a transition to post-quantum cryptographic primitives worldwide. The post-quantum cryptographic primitive standardization effort led by the US NIST has recently selected the asymmetric encryption primitive Kyber as its candidate for standardization. It has also indicated NTRU, another lattice-based primitive, as a valid alternative if intellectual property issues are not solved. Finally, a more conservative alternative to NTRU, NTRUPrime was also considered as an alternate candidate, due to its design choices which remove the possibility for a large set of attacks preemptively. All the aforementioned asymmetric primitives provide good performances, and are prime choices provide IoT devices with post-quantum confidentiality services. In this work, we propose a unified design for a hardware accelerator able to speed up the computation of polynomial multiplications, the workhorse operation in all of the aforementioned cryptosystems, managing the differences in the polynomial rings of the cryptosystems. Our design is also able to outperform the state of the art designs tailored specifically for NTRU, and provide latencies similar to the symmetric cryptographic elements required by the scheme for Kyber and NTRUPrime